1. Field of the Invention
The present invention relates to a non-volatile memory circuit capable of electrical writing and reading.
2. Description of the Related Art
There is known a semiconductor integrated circuit including a bleeder resistor circuit capable of being trimmed by a memory. Hitherto, the bleeder resistance is adjusted by a method of mechanically cutting the fuse formed in parallel to the bleeder resistor with use of laser light or the like. The trimming of the bleeder resistor can accordingly be performed only before assembling a package. The use of a memory for trimming the bleeder resistor, on the other hand, enables electrical trimming even after the assembly. The following two typical benefits are obtained.
1. Users' requests for quick delivery can be accommodated because the trimming is carried out for the bleeder resistor in the package before shipment.
2. High precision can be achieved because the trimming covers package-related shift that occurs in assembling the package.
In general, once the bleeder resistor is trimmed, there is no need to alter information. As a trimming memory, an ultraviolet erasable, non-volatile erasable programmable read only memory (EPROM) is accordingly used as a one-time programmable (OTP) memory. Further, unlike a memory IC, the memory for trimming the bleeder resistor requires small memory capacity. As compared to the memory IC, high integration and high-speed operation of a memory cell are not required. Consequently, the typical challenges for the trimming memory include downsizing a peripheral circuit for controlling the memory, achieving lower voltage operation, and utilizing the existing manufacturing process.
As an ultraviolet erasable non-volatile EPROM, a non-volatile EPROM for writing information with use of hot carriers has hitherto been known. Particularly at present, the mainstream of the non-volatile memory for writing information with the use of hot carriers is an N-channel non-volatile EPROM. One of the reasons is that the N-channel non-volatile EPROM has a higher operating speed than a P-channel EPROM.
However, because the memory for trimming the bleeder resistor has small capacity and is not required to alter information once the information is written in trimming as described above, there is no problem even if the operating speed is lower than that of the memory IC. Further, in the P-channel EPROM, without applying such a high potential that causes avalanche breakdown between the substrate and the drain, drain avalanche hot electrons (DAHEs) are generated by applying a relatively low voltage and injected into a floating gate, to thereby change a threshold voltage and perform writing. Thus, it is considered that the P-channel non-volatile EPROM is more suitable for the memory for trimming the bleeder resistor.
The structure of a conventional P-channel non-volatile EPROM for writing information with the use of hot carriers is described below with reference to a cross-sectional view illustrated in FIG. 3.
In FIG. 3, an N-type well 8 is formed along one principal surface of a P-type semiconductor substrate 7 in which an element isolation region 9 is selectively formed. In the N-type well 8, impurities having P-type conductivity are heavily diffused to form a source region 10 and a drain region 11. On the substrate in which the source region 10 and the drain region 11 are formed, a floating gate 13 is formed through intermediation of a gate oxide film 12. On the floating gate 13, a control gate 15 is formed through intermediation of a second insulating film 14. The conventional non-volatile EPROM is configured in this way. The structure of electrode wiring and other members to be formed in subsequent processes (metal wiring and protective film) is the same as that in a commonly used semiconductor device, and hence its detailed description is omitted.
In the conventional non-volatile EPROM, it is said to be necessary to apply a high voltage to the drain and the control gate in writing in order to generate hot electrons to be injected into the floating gate. As described above for the challenges for the trimming memory, if the voltage in writing is high, the peripheral circuit needs to have a high withstand voltage, and the element structure becomes complicated in order to realize the high withstand voltage. As a result, there arise problems in that the area and the number of processes are increased. Accordingly, the operating voltage is required to be lower. If the write voltage is lowered, however, there is a problem in that the generation efficiency of hot carriers is reduced due to the low operating voltage so that a write period and an erase period become longer. Accordingly, write characteristics in the low voltage operation are required to be improved.
As means for improving the write characteristics, there is disclosed a technology for improving the write characteristics as follows. Irregularities are provided on an upper surface of the floating gate to increase the capacitance between the floating gate and the control gate and thereby increasing the potential of the floating gate (see, for example, Japanese Published Patent Application H05-55605).
However, when the method described in Japanese Published Patent Application H05-55605 is used to improve the write characteristics, the write characteristics can be improved for an N-channel EPROM and the method is effective, but the method is not effective for a P-channel EPROM.
Hitherto, in the case of the P-channel EPROM, similarly to the N-channel EPROM, a high voltage is applied to the drain and the control gate in writing (see, for example, Japanese Published Patent Application 2001-257324). However, because an optimum floating gate voltage for writing in the P-channel EPROM is set in the vicinity of a threshold of a memory element, the write characteristics cannot be improved even when the floating gate potential is increased in writing in the P-channel EPROM.